Image sensor and devices having the same

ABSTRACT

An image sensor according to an example embodiment of includes a first pixel and a second pixel in a first row. The first pixel includes a first photoelectric conversion element at a first depth in a semiconductor substrate and the first photoelectric conversion element is configured to convert a first visible light spectrum into a first photo charge, and the second pixel includes a second photoelectric conversion element at a second depth from the first depth in the semiconductor substrate, the second photoelectric conversion element is at least partially overlapped by the first photoelectric conversion element in a vertical direction, and the second photoelectric conversion element is configured to convert a second visible light spectrum into a second photo charge.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119(a) from KoreanPatent Application No. 10-2013-0127545 filed on Oct. 25, 2013, thedisclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Example embodiments of inventive concepts relate to a complementarymetal oxide semiconductor (CMOS) image sensor.

The CMOS image sensor is a solid-state image sensing device using acomplementary metal oxide semiconductor (CMOS). The CMOS image sensorhas a lower manufacturing cost than a charge coupled device (CCD) imagesensor including a high-voltage analog circuit, and consumes less powerdue to the small size thereof.

Recently, as the CMOS image sensor has improved in performance, the CMOSimage sensor has been used in various consumer electronics in additionto portable electronic devices such as smart phones and digital cameras.The CMOS image sensor includes a photo-electric conversion elementconfigured to receive light and convert the light into an electricalsignal. The more light received by the photo-electric conversionelement, the better the photo sensitivity of the CMOS image sensor.

As the CMOS image sensor has recently become smaller, that thesensitivity of the CMOS image sensor lowers. For example, as a pixel ofan image sensor becomes smaller, a photo-electric conversion element ofthe pixel decreases in size and the sensitivity of the CMOS image sensoris affected by the size of the pixel.

SUMMARY

An example embodiment of inventive concepts is directed to an imagesensor, including a first pixel and a second pixel arranged in a firstrow. The first pixel includes a first photoelectric conversion elementat a first depth in a semiconductor substrate and the firstphotoelectric conversion element is configured to convert a firstvisible light spectrum into a first photo charge, and the second pixelincludes a second photoelectric conversion element at a second depthfrom the first depth in the semiconductor substrate, the secondphotoelectric conversion element is at least partially overlapped by thefirst photo-electric conversion element in a vertical direction, and thesecond photoelectric conversion element is configured to convert asecond visible light spectrum into a second photo charge.

The image sensor further includes a third pixel and a fourth pixelarranged in a second row. The third pixel includes a third photoelectricconversion element at a second depth and the third photoelectricconversion element is configured to convert the second visible lightspectrum into a third photo charge, and the fourth pixel includes afourth photoelectric conversion element at a third depth from the seconddepth in the semiconductor substrate, the fourth photoelectricconversion element is at least partially overlapped by the thirdphotoelectric conversion element in a vertical direction, and the fourthphotoelectric conversion element is configured to convert a thirdvisible light spectrum into a fourth photo charge.

According to an example embodiment, the first pixel and the third pixelshare a first floating diffusion node in the semiconductor substrate,and the second pixel and the fourth pixel share a second floatingdiffusion node in the semiconductor substrate.

According to another example embodiment, the first pixel, the secondpixel, the third pixel, and the fourth pixel share a floating diffusionnode in the semiconductor substrate.

An overlapped region of the first photoelectric conversion element andthe second photoelectric conversion element is shorter than a length ofthe first photoelectric conversion element, and an overlapped region ofthe third photoelectric conversion element and the fourth photoelectricconversion element is shorter than a length of the third photoelectriccon version element.

The image sensor may be embodied in a backside illumination (BSI) imagesensor. An image processing device according to an example embodiment ofinventive concepts includes the image sensor and a processor configuredto control the image sensor.

A portable electronic device according to an example embodiment ofinventive concepts includes the image sensor and an applicationprocessor controlling the image sensor.

At least another example embodiment discloses and image sensor includinga first pixel and a second pixel, the first pixel including a firstphotoelectric conversion element in a semiconductor substrate, and thesecond pixel including, a second photoelectric conversion element in thesemiconductor substrate, at least a portion of the first photoelectricconversion element covers at least a portion of the second photoelectricconversion element in a vertical direction.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects and advantages of inventive concepts willbecome apparent and more readily appreciated from the followingdescription of the embodiments, taken in conjunction with theaccompanying drawings of which:

FIG. 1 is a schematic block view of an image processing device accordingto an example embodiment of inventive concepts;

FIG. 2 represents an example embodiment of a plan view of a pixel groupinclude in a pixel array of FIG. 1;

FIGS. 3A and 3B each represent a cross-sectional view taken along a lineXI-XI′ and a cross-sectional view taken along a line X2-X2′ of FIG. 2;

FIG. 4 represents a circuit view including a first pixel and a thirdpixel which are illustrated in FIG. 2 and share a first floatingdiffusion node;

FIG. 5 represents a circuit view including a second pixel and a fourthpixel which are illustrated in FIG. 2 and share a second floatingdiffusion node;

FIG. 6 represents another example embodiment of a plan view of a pixelgroup included in the pixel array of FIG. 1;

FIGS. 7A and 7B each represent a cross-sectional view taken along a lineX4-X4′ of FIG. 6 and a cross-sectional view taken along a line X4-X4′ ofFIG. 6;

FIG. 8 represents a circuit view including four pixels which areillustrated in FIG. 6 and share one floating diffusion node; and

FIG. 9 is a schematic block view of an image processing device accordingto another example embodiment of inventive concepts.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Inventive concepts now will be described more fully hereinafter withreference to the accompanying drawings, in which example embodiments areshown. Inventive concepts may, however, be embodied in many differentforms and should not be construed as limited to example embodiments setforth herein. Rather, example embodiments are provided so that thisdisclosure will be thorough and complete, and will fully convey thescope of inventive concepts to those skilled in the art. In thedrawings, the size and relative sizes of layers and regions may beexaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. As used herein, the term “and/or” includesany and all combinations of one or more of the associated listed itemsand may be abbreviated as “/”.

It will be understood that, although the terms first, second, etc, maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first signal could be termed asecond signal, and, similarly, a second signal could be termed a firstsignal without departing from the teachings of the disclosure.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of inventiveconcepts. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” or “includes” and/or “including” whenused in this specification, specify the presence of stated features,regions, integers, steps, operations, elements, and/or components, butdo not preclude the presence or addition of one or more other features,regions, integers, steps, operations, elements, components, and/orgroups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and/orthe present application, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

FIG. 1 is a schematic block view of an image processing device accordingto an example embodiment of inventive concepts. Referring to FIG. 1, animage processing device 1000 may be embodied in a portable electronicdevice such as a digital camera, a mobile phone, a smart phone, a tabletpersonal computer (PC), a personal digital assistant (PDA), a mobileinternet device (MID), or a wearable computer.

The image processing device 1000 includes a CMOS image sensor 100, adigital signal processor (DSP) 200, a display 300, and an optical lens500. According to an example embodiment, the image processing device1000 may not include the optical lens 500.

The CMOS image sensor 100 may generate image data IDATA for a subjectincident through the optical lens 500. The CMOS image sensor 100 may beembodied in a backside illumination (BSI) image sensor.

The CMOS image sensor 100 may include an active pixel sensor array 110,a row driver 120, a correlated double sampling (CDS) block 130, ananalog-to-digital converting (ADC) block 140, a ramp generator 150, atiming generator 160, a control register block 170, and a buffer 180.

The CMOS image sensor 100 may sense an image of the subject 400 capturedor incident through the optical lens 500, and generate image data IDATAcorresponding to a result of the sensing.

The active pixel sensor array 110 includes a plurality of pixel groups10 arranged in a matrix shape. A pixel group 10A of FIG. 2 and a pixelgroup 10B of FIG. 6 are collectively referred to as the pixel group 10.Accordingly, the pixel group 10 includes a plurality of pixels.

The row driver 120 may generate control signals which may control anoperation of each of a plurality of pixels included in the active pixelsensor array 110. The CDS block 130 may perform a correlated doublesampling operation on a pixel signal output from each of the pluralityof pixels using a ramp signal output from the ramp generator 150, andoutput a correlated double sampled pixel signal. The ADC block 140 mayconvert each of the correlated double sampled pixel signals into eachdigital signal by the CDS block 130.

The timing generator 160 may control the row driver 120, the CDS block130, the ADC block 140, and/or the ramp generator 150 based on outputsignals of the control register block 170.

The control register block 170 may store control bits which may controlan operation of the timing generator 160, the ramp generator 150, and/orthe buffer 180. The buffer 180 may buffer digital signals output fromthe ADC block 140 and generate image data IDATA according to a result ofthe buffering. A DSP 200 may output image signals corresponding to theimage data IDATA output from the CMOS image sensor 100 to a display 300.

The DSP 200 includes an image signal processor (ISP) 210, a cameracontroller 220, and an interface (I/F) 230.

The ISP 210 receives the image data IDATA output from the buffer 180,processes the received image data IDATA to be visible to people, andoutputs the processed image data to the display 300 through the I/F 230.

The camera controller 220 controls an operation of the control registerblock 170. The camera controller 220 controls an operation of the CMOSimage sensor 100, e.g., the control register block 170, using aprotocol, e.g., an inter-integrated circuit (I2C); however, a technicalconcept of the present inventive concepts is not limited thereto.

In FIG. 1, it is illustrated that the ISP 210 is embodied in the DSP200, however the ISP 210 may be embodied in the CMOS image sensor 100according to an example embodiment. Moreover, the CMOS image sensor 100and the ISP 210 may be embodied in one package, e.g., a multi-chippackage (MCP) or a package on package (PoP).

FIG. 2 represents an example embodiment of a plan view of a pixel groupincluded in the pixel array in FIG. 1. Referring to FIG. 2, a pixelgroup 10A according to an example embodiment of the pixel group 10 ofFIG. 1 may include a first pixel 10-1 and a second pixel 10-2 arrangedin a first row, and a third pixel 10-3 and a fourth pixel 10-4 arrangedin a second row.

That is, the first pixel 10-1 and the second pixel 10-2 may berepeatedly arranged in the first row, and the third pixel 10-3 and thefourth pixel 10-4 may be repeatedly arranged in the second row.Moreover, the first pixel 10-1 and the second pixel 10-2 may berepeatedly arranged in an odd numbered row, and the third pixel 10-3 andthe fourth pixel 10-4 may be repeatedly arranged in an even numberedrow. For convenience of description in FIG. 2, four pixels 10-1 to 10-4are illustrated in detail.

The plan view of FIG. 2 projects and represents each component, e.g.,each photoelectric conversion element B, G, and R, each transistor TX1,TX2, TX3, TX4, RX1, RX2, SX1, SX2, DX1, and DX2, each floating diffusionnode FD1 and FD2, a plug, and/or a metal contact onto the same plane.

For example, when viewed from the photoelectric conversion element, B isa photoelectric conversion element PD1 which photoelectrically convertsa blue spectrum into a first photo charge, G is a photoelectricconversion element PD2 and PD3 which photoelectrically converts a greenspectrum into second and third photo charges, respectively, and R is aphotoelectric conversion element PD4 which photoelectrically converts ared spectrum into a fourth photo charge. Here, a spectrum is a set ofwaves.

A structure and an operation of each component included in the plan viewof FIG. 2 will be described in detail referring to FIGS. 2 to 5.

The first pixel 10-1 includes a first photoelectric conversion elementPD1 which converts a first visible light spectrum, e.g., the bluespectrum, into the first photo charge(s), a first transmissiontransistor TX1, a first floating diffusion node FD1, a first resettransistor RX1, a first drive transistor DX1, and a first selectiontransistor SX1.

The second pixel 10-2 includes a second photoelectric conversion elementPD2 which converts a second visible light spectrum, e.g., the greenspectrum, into the second photo charge(s), a second transmissiontransistor TX2, a second floating diffusion node FD2, a second resettransistor RX2, a second drive transistor DX2, and a second selectiontransistor SX2.

The third pixel 10-3 includes a third photoelectric conversion elementPD3 which converts the second visible light spectrum, e.g., the greenspectrum, into the third photo charge(s), a third transmissiontransistor TX3, the first floating diffusion node FD1, the first resettransistor RX1, the first drive transistor DX1, and the first selectiontransistor SX1.

The fourth pixel 10-4 includes a fourth photoelectric conversion elementPD4 which converts a third visible light spectrum, e.g., the redspectrum, into the fourth photo charge(s), a fourth transmissiontransistor TX4, the second floating diffusion node FD2, the second resettransistor RX2, the second drive transistor DX2, and the secondselection transistor SX2.

The first pixel 10-1 and the third pixel 10-3 share the first floatingdiffusion node FD1, the first reset transistor RX1, the first drivetransistor DX1, and the first selection transistor SX1 as illustrated inFIG. 4.

The second pixel 10-2 and the fourth pixel 10-4 share the secondfloating diffusion node FD2, the second reset transistor RX2, the seconddrive transistor DX2, and the second selection transistor SX2 asillustrated in FIG. 5.

FIGS. 3A and 3B each represent a cross-sectional view taken along a lineXI-XI′ and a cross-sectional view taken along a line X2-X2′ of FIG. 2. AXI-XI′ cross-sectional view illustrated in FIG. 3A includes the firstphotoelectric conversion element PD1, the second photoelectricconversion element PD2, a readout circuit region 20, a semiconductorsubstrate 30, and a plurality of charge transmission paths PL1, PL2, andPL3. In some cases, a charge transmission path performing a function oftransmitting a charge may be referred to as a channel or a plug.

For example, in the read out circuit region 20, processing circuitswhich may process charges output from a corresponding photoelectricconversion element, e.g., a corresponding floating diffusion node andone or more transistors, may be embodied.

The first photoelectric conversion element PD1 may be formed at a firstdepth H1 in the semiconductor substrate 30, and the second photoelectricconversion element PD2 may be formed at a second depth H2 from the firstdepth in the semiconductor substrate 30. Here, the first depth H1 is onthe basis of a bottom surface of the semiconductor substrate 30.

The second photoelectric conversion element PD2, over the firstphotoelectric conversion element PD1, may partially overlap the firstphotoelectric conversion element PD1 in a vertical direction. In otherwords, a portion of the second photoelectric conversion element PD2covers a portion of the first photoelectric conversion element PD1 andvice versa.

When the first photoelectric conversion element PD1 and the secondphotoelectric conversion element PD2 partially overlap each other, anoverlapped region L2 of the first photoelectric conversion element PD1and the second photoelectric conversion element PD2 may be embodiedshorter than the length of the first photoelectric conversion elementPD1. For example, there may be L2<(0.5*L1).

The X2-X2′ cross-sectional view 10A-2 illustrated in FIG. 3B includesthe first photoelectric conversion element, a third photoelectricconversion element PD3, a fourth photoelectric conversion element PD4, areadout circuit region 20 a, the semiconductor substrate 30, and aplurality of charge transmission paths PL4 and PL5.

The third photoelectric conversion element PD3 may be formed at thesecond depth H2 in the semiconductor substrate 30, and the fourthphotoelectric conversion element PD4 may be formed at a third depth H3from the second depth H2 in the semiconductor substrate 30. The fourthphotoelectric conversion element PD4, over the third photoelectricconversion element PD3, may partially overlap the third photoelectricconversion element. PD3 in a vertical direction. In other words, aportion of the fourth photoelectric conversion element PD4 covers aportion of the third photoelectric conversion element PD3 and viceversa.

When the third photoelectric conversion element PD3 and the fourthphotoelectric conversion element PD4 overlap each other, each overlappedregion L4 and L5 of the third photoelectric conversion element PD3 andthe fourth photoelectric conversion element PD4 may be embodied shorterthan the length L3 of the third photoelectric conversion element PD3.For example, there may be L4<(0.5*L3) or L5<(0.5*L3).

For example, in the readout circuit region 20 a, processing circuitswhich may process charges output from a corresponding photoelectricconversion element, e.g., a corresponding floating diffusion node andone or more transistors, may be embodied.

When the semiconductor substrate 30 is doped with one of an n-typeimpurity and a p-type impurity, each photoelectric conversion elementPD1 to PD4 may be doped with the other of the n-type impurity and thep-type impurity.

FIG. 4 represents a circuit view including a first pixel and a thirdpixel which are illustrated in FIG. 2 and share a first floatingdiffusion node. Referring to FIGS. 2, 3, and 4, a two-shared pixel 10A-4includes the first pixel 10-1 and the third pixel 10-3.

Each pixel 10-1 and 10-3 shares the first floating diffusion node PD1,the first reset transistor RX1, the first drive transistor DX1, and thefirst selection transistor SX1.

The first reset transistor RX1 resets the first floating diffusion nodeFD1 in response to a reset signal RS1 output from the row driver 120.The first transmission transistor TX1 transmits charges accumulated inthe first photoelectric conversion element PD1 to the first floatingdiffusion node MI in response to a first transmission control signal TS1output from the row driver 120.

The third transmission transistor TX3 transmits charges accumulated inthe third photoelectric conversion element PD3 to the first floatingdiffusion node FD1 in response to a third transmission control signalTS3 output from the row driver 120.

A generation timing of each transmission control signal TS1 and TS3 maybe variously designed according to a design specification of the imageprocessing device 1000.

The first drive transistor DX1 may perform a source following operationbased on a voltage corresponding to the charges accumulated in the firstfloating diffusion node FD1 and a supply voltage VDD. The firstselection transistor SX1 may transmit a signal, e.g., a pixel signal,output from the first drive transistor DX1 to a column line COL inresponse to a first selection signal SEL1.

FIG. 5 represents a circuit view including a second pixel and a fourthpixel which are illustrated in FIG. 2 and share a second floatingdiffusion node.

Referring to FIGS. 2, 3, and 5, a two-shared pixel 10A-5 includes thesecond pixel 10-2 and the fourth pixel 10-4.

Each pixel 10-2 and 10-4 shares the second floating diffusion node FD2,the second reset transistor RX2, the second drive transistor DX2, andthe second selection transistor SX2.

The second reset transistor RX2 resets the second floating diffusionnode FD2 in response to a second reset signal RS2 output from the rowdriver 120. The second transmission transistor TX2 transmits the chargesaccumulated in the second photoelectric conversion element PD2 to thesecond floating diffusion node FD2 in response to a second transmissioncontrol signal TS2 output from the row driver 120.

The fourth transmission transistor TX4 transmits charges accumulated inthe fourth photoelectric conversion element PD4 to the second floatingdiffusion node FD2 in response to a fourth transmission control signalTS4 output from the row driver 120. A generation timing of eachtransmission control signal TS2 and TS4 may be variously designedaccording to a design specification of the image processing device 1000.

The second drive transistor DX2 may perform the source followingoperation based on a voltage corresponding to the charges accumulated inthe second floating diffusion node FD2 and the supply voltage VDD.

The second selection transistor SX2 may transmit a signal, e.g., a pixelsignal, output from the second drive transistor DX2 to the column lineCOL in response to the second selection signal SEL2.

Each photoelectric conversion element PD1, PD2, PD3, and PD4 may beembodied in a photo diode, a photo transistor, a photo gate, a pinnedphoto diode (PPD), or a combination of these.

FIG. 6 represents another example embodiment of the plan view of a pixelgroup included in the pixel array of FIG. 1. Referring to FIG. 6, apixel group 10B according to another example embodiment of the pixelgroup 10 of FIG. 1 may include a first pixel 10-1 a and a second pixel10-2 a arranged in a first row, and a third pixel 10-3 a and a fourthpixel 10-4 a arranged in a second row. That is, the first pixel 10-1 aand the second pixel 10-2 a may be repeatedly arranged in the first row;and the third pixel 10-3 a and the fourth pixel 10-4 a may be repeatedlyarranged in the second row.

Moreover, the first pixel 10-1 a and the second pixel 10-2 a may berepeatedly arranged in an odd numbered row, and the third pixel 10-3 aand the fourth pixel 10-4 a may be repeatedly arranged in an evennumbered row.

For convenience of description in FIG. 6, four pixels 10-1 a to 10-4 aare described in detail. The plan view of FIG. 6 projects and representseach component, e.g., each photoelectric conversion element B, G, and R,each transistor TX1 a, TX2 a, TX3 a, TX4 a, RX3, DX3, and SX3, afloating diffusion node FD, a plug, and/or a metal contact onto the sameplane.

As described above, when viewed from the photoelectric conversionelement, B is a photoelectric conversion element PD1 whichphotoelectrically converts the blue spectrum, G is a photoelectricconversion element PD2 and PD3 which photoelectrically converts thegreen spectrum, and R is a photoelectric conversion element PD4 whichphotoelectrically converts the red spectrum.

A structure and an operation of each component included in the plan viewof FIG. 6 will be described in detail referring to FIGS. 6 to 8.

The first pixel 10-1 a includes the first photoelectric conversionelement PD1 which converts the first visible light spectrum, e.g., theblue spectrum, into a first photo charge(s), a first transmissiontransistor TX1 a, the floating diffusion node FD, a third resettransistor RX3, a third drive transistor DX3, and a third selectiontransistor SX3.

The second pixel 10-2.a includes the second photoelectric conversionelement PD2 which converts the second visible light spectrum, e.g., thegreen spectrum, into a second photo charge(s), a second transmissiontransistor TX2 a, the floating diffusion node FD, the third resettransistor RX3, the third drive transistor DX3, and the third selectiontransistor SX3.

The third pixel 10-3 a includes the third photoelectric conversionelement PD3 which converts the second visible light spectrum, e.g., thegreen spectrum, into a third photo charge(s), a third transmissiontransistor TX3 a, the floating diffusion node FD, the third resettransistor RX3, the third drive transistor DX3, and the third selectiontransistor SX3.

The fourth pixel 10-4 a includes the fourth photoelectric conversionelement PD4, which converts the third visible light spectrum, e.g., thered spectrum, into a fourth photo charge(s), a fourth transmissiontransistor TX4 a, the floating diffusion node FD, the third resettransistor RX3, the third drive transistor DX3, and the third selectiontransistor SX3.

The first pixel 10-1 a, the second pixel 10-2 a, the third pixel 10-3 a,and the fourth pixel 10-4 a share the floating diffusion node FD, thethird reset transistor RX3, the third drive transistor DX3, and thethird selection transistor SX3.

FIGS. 7A and 7B each represent a cross-sectional view taken along a lineX4-X4′ of FIG. 6 and a cross-sectional view taken along a line X4 X4′ ofFIG. 6. The X3-X3′ cross-sectional view 10B-1 illustrated in FIG. 7Aincludes the first photoelectric conversion element PD1, the thirdphotoelectric conversion element PD3, the fourth photoelectricconversion element PD4, a readout circuit region 20 b, a semiconductorsubstrate 30 a, and a plurality of charge transmission paths PL6 andPL7.

The first photoelectric conversion element PD1 may be formed at a firstdepth H1 in the semiconductor substrate 30 a, the third photoelectricconversion element PD3 may be formed at a second depth H2 from the firstdepth H1 in the semiconductor substrate 30 a, and the fourthphotoelectric conversion element PD4 may be formed at the third depth H3from the second depth H2 in the semiconductor substrate 30 a. Here, thefirst depth H1 is on the basis of the bottom surface of semiconductorsubstrate 30 a.

The third photoelectric conversion element PD3, over the firstphotoelectric conversion element PD1, may partially overlap the firstphotoelectric conversion element PD1 in a vertical direction. In otherwords, a portion of the third photoelectric conversion element PD1covers a portion of the first photoelectric conversion element PD1 andvice versa.

When the first photoelectric conversion element PD1 and the thirdphotoelectric conversion element PD3 partially overlap each other, anoverlapped region of the first photoelectric conversion element PD1 andthe third photoelectric conversion element PD3 may be embodied shorterthan the length of the first photoelectric conversion element PD1. Theoverlapped region may be embodied shorter than a half of the length.

The fourth photoelectric conversion element PD4 embodied over the thirdphotoelectric conversion element PD3 may partially overlap the thirdphotoelectric conversion element PD3 in a vertical direction. In otherwords, a portion of the fourth photoelectric conversion element PD4covers a portion of the third photoelectric conversion element PD3 andvice versa. An overlapped region L7 of the third photoelectricconversion element PD3 and the fourth photoelectric conversion elementPD4 may be embodied shorter than the length L6 of the thirdphotoelectric conversion element PD3. For example, there may beL7<(0.5*L6).

For example, in the readout circuit region 20 b, processing circuitswhich may process charges output from a corresponding photoelectricconversion element, e.g., a corresponding floating diffusion node andone or more transistors, may be embodied.

The X4-X4′ cross-sectional view 10B-2 illustrated in FIG. 7B includesthe first photoelectric conversion element PD1 the third photoelectricconversion element PD3, the fourth photoelectric conversion element PD4,a readout circuit region 20 c, the semiconductor substrate 30 a, and aplurality of charge transmission paths PL8 and PL9.

The first photoelectric conversion element PD1 may be formed at thefirst depth H1 in the semiconductor substrate 30 a, the thirdphotoelectric conversion element PD3 may be formed at the second depthH2 from the first depth H1 in the semiconductor substrate 30 a, and thefourth photoelectric conversion element. PD4 may be formed at the thirddepth 113 from the second depth H2 in the semiconductor substrate 30 a.

For example, in the readout circuit region 20 c, processing circuitswhich may process charges output from a corresponding photoelectricconversion element, e.g., a corresponding floating diffusion node andone or more transistors, may be embodied.

FIG. 8 represents a circuit view including four pixels which areillustrated in FIG. 6 and share one floating diffusion node. Referringto FIGS. 6 to 8, a four-shared pixel 10B-3 includes the first pixel 10-1a, the second pixel 10-2 a, the third pixel 10-3 a, and the fourth pixel10-4 a.

Each pixel 10-1 a to 10-4 a shares the floating diffusion node FD, thethird reset transistor RX3, the third drive transistor DX3, and thethird selection transistor SX3.

The third reset transistor RX3 resets the floating diffusion node FD inresponse to the third reset signal RS3 output from the row driver 120.

The first transmission transistor TX1 a transmits the chargesaccumulated in the first photoelectric conversion element PD1 to thefloating diffusion node FD in response to a first transmission controlsignal TS1 output from the row driver 120. The second transmissiontransistor TX2 a transmits the charges accumulated in the secondphotoelectric conversion element PD2 to the floating diffusion node FDin response to a second transmission control signal TS2 output from therow driver 120.

The third transmission transistor TX3 a transmits the chargesaccumulated in the third photoelectric conversion element PD3 to thefloating diffusion node FD in response to a third transmission controlsignal TS3 output from the row driver 120. The fourth transmissiontransistor TX4 a transmits the charges accumulated in the fourthphotoelectric conversion element PD4 to the floating diffusion node FDin response to a fourth transmission control signal TS4 output from therow driver 120.

A generation timing of each transmission control signal TS1, TS2, TS3,and TS4 may be variously designed according to a design specification ofthe image processing device 1000.

The third drive transistor DX3 may perform the source followingoperation based on a voltage corresponding to the charges accumulated inthe floating diffusion node FD and the supply voltage VDD. The thirdselection transistor SX3 may transmit a signal, e.g., a pixel signal,output from the third drive transistor DX3 to the column line COL inresponse to the third selection signal SEL3.

FIG. 9 is a schematic block view of an image processing device accordingto another example embodiment of inventive concepts. Referring to FIGS.1 to 9, an image processing device 900 may be embodied in a portableelectronic device which may use or support a mobile industry processorinterface (MIPI®) standard or an Embedded DisplayPort (eDP) standard.

The portable electronic device may be embodied in a laptop computer, apersonal digital assistant (PDA), a portable media player (PMP), amobile phone, a smart phone, a tablet personal computer (PC), a digitalcamera, a mobile internet device (MID), or a wearable computer.

The image processing device 900 includes an application processor (AP)910, a CMOS image sensor 100, and a display 300. A camera serialinterface (CSI) host 913 embodied in the AP 910 may perform a serialcommunication with a CSI device 101 of a CMOS image sensor 100 through acamera serial interface CSI.

According to an example embodiment, a de-serializer DES may be embodiedin the CSI host 913, and a serializer SER may be embodied in the CSIdevice 101.

The CMOS image sensor 100 may be the CMOS image sensor 100 describedreferring to FIGS. 1 to 8. A display serial interface (DSI) host 911embodied in the AP 910 may perform the serial communication with a DSIdevice 310 of the display 300 through a display serial interface.

According to an example embodiment, a serializer SER may be embodied inthe DSI host 911, and a de-serializer DES may be embodied in the DSIdevice 310. Each of the deserializer DES and the serializer SER mayprocess an electrical signal or an optical signal.

The image processing device 900 may further include a radio frequency(RF) chip 940 which may communicate with the AP 910. A physical layer915 of the AP 910 and a PHY 941 of the RF chip 940 may transmit orreceive data according to MIPI DigRF.

The image processing device 900 may further include a GPS receiver 950,a memory 951 such as a dynamic random access memory (DRAM), a datastorage device 953 embodied in a non-volatile memory such as a NANDflash memory, a microphone 955, and a speaker 957.

The image processing device 900 may communicate with an external deviceusing at least one communication protocol or communication standard,e.g., worldwide interoperability for microwave access (WiMAX) 959,Wireless LAN (WLAN) 961, ultra-wideband (UWB) 963, or long termevolution (LTE™) 965. The image processing device 900 may communicatewith an external device using Bluetooth or WiFi.

An image sensor according to an example embodiment of inventive conceptsmay increase a size of a photoelectric conversion element formed in asemiconductor device to improve the sensitivity of a pixel including thephotoelectric conversion element and to increase full-well capacity. Theimage sensor according to an example embodiment of inventive conceptsdoes not include a color filter, thereby preventing light loss caused bythe color filter.

Although example embodiments of inventive concepts have been shown anddescribed, it will be appreciated by those skilled in the art thatchanges may be made in example embodiments without departing from theprinciples and spirit of inventive concepts, the scope of which isdefined in the appended claims and their equivalents.

What is claimed is:
 1. An image sensor comprising: a first pixel and asecond pixel in a first row, wherein the first pixel includes a firstphotoelectric conversion element at a first depth in a semiconductorsubstrate and the first photoelectric conversion element is configuredto convert a first visible light spectrum into a first photo charge, andthe second pixel includes a second photoelectric conversion element at asecond depth from the first depth in the semiconductor substrate, aportion of the second photoelectric conversion element is overlapped bya portion of the first photoelectric conversion element in a verticaldirection, and the second photoelectric conversion element is configuredto convert a second visible light spectrum into a second photo charge,the portion of the second photoelectric conversion element being lessthan the entire second photoelectric conversion element and the portionof the first photoelectric conversion element being less than the entirefirst photoelectric conversion element.
 2. The image sensor of claim 1,further comprising: a third pixel and a fourth pixel in a second row,wherein the third pixel includes a third photoelectric conversionelement at the second depth and the third photoelectric conversionelement is configured to convert the second visible light spectrum intoa third photo charge, and the fourth pixel includes a fourthphotoelectric conversion element at a third depth from the second depthin the semiconductor substrate, the fourth photoelectric conversionelement is at least partially overlapped by the third photoelectricconversion element in a vertical direction, and the fourth photoelectricconversion element is configured to convert a third visible lightspectrum into a fourth photo charge.
 3. The image sensor of claim 2,wherein the first pixel and the third pixel share a first floatingdiffusion node in the semiconductor substrate, and the second pixel andthe fourth pixel share a second floating diffusion node in thesemiconductor substrate.
 4. The image sensor of claim 2, wherein thefirst pixel, the second pixel, the third pixel, and the fourth pixelshare a floating diffusion node in the semiconductor substrate.
 5. Animage sensor comprising: a first pixel and a second pixel in a firstrow, wherein the first pixel includes a first photoelectric conversionelement at a first depth in a semiconductor substrate and the firstphotoelectric conversion element is configured to convert a firstvisible light spectrum into a first photo charge, and the second pixelincludes a second photoelectric conversion element at a second depthfrom the first depth in the semiconductor substrate, the secondphotoelectric conversion element is at least partially overlapped by thefirst photoelectric conversion element in a vertical direction, and thesecond photoelectric conversion element is configured to convert asecond visible light spectrum into a second photo charge, wherein thesemiconductor substrate is doped with one of a first impurity and asecond impurity; and the first pixel and the second pixel are doped withanother of the first impurity and the second impurity.
 6. The imagesensor of claim 2, wherein the image sensor is a backside illumination(BSI) image sensor.
 7. An image processing device comprising: the imagesensor of claim 1; and a processor configured to control the imagesensor.
 8. The image processing device of claim 7, wherein the imagesensor further includes a third pixel and a fourth pixel in a secondrow, wherein the third pixel includes a third photoelectric conversionelement at the second depth and the third photoelectric conversionelement is configured to convert the second visible light spectrum intoa third photo charge, and the fourth pixel includes a fourthphotoelectric conversion element at a third depth from the second depthin the semiconductor substrate, the fourth photoelectric conversionelement is at least partially overlapped by the third photoelectricconversion element in a vertical direction, and the fourth photoelectricconversion element is configured to convert a third visible lightspectrum into a fourth photo charge.
 9. The image processing device ofclaim 8, wherein the first pixel and the third pixel share a firstfloating diffusion node in the semiconductor substrate, and the secondpixel and the fourth pixel share a second floating diffusion node in thesemiconductor substrate.
 10. The image processing device of claim 8,wherein the first pixel, the second pixel, the third pixel, and thefourth pixel share a floating diffusion node in the semiconductorsubstrate.
 11. A portable electronic device comprising: the image sensorof claim 1; and an application processor configured to control the imagesensor.
 12. The portable electronic device of claim 11, wherein theimage sensor further includes a third pixel and a fourth pixel in asecond row, and the third pixel includes a third photoelectricconversion element at the second depth and the third photoelectricconversion element is configured to convert the second visible lightspectrum into a third photo charge, and the fourth pixel includes afourth photoelectric conversion element at a third depth from the seconddepth in the semiconductor substrate, the fourth photoelectricconversion element is at least partially overlapped by the thirdphotoelectric conversion element in a vertical direction, and the fourthphotoelectric conversion element is configured to convert a thirdvisible light spectrum into a fourth photo charge.
 13. The portableelectronic device of claim 12, wherein the first pixel and the thirdpixel share a first floating diffusion node in the semiconductorsubstrate, and the second pixel and the fourth pixel share a secondfloating diffusion node in the semiconductor substrate.
 14. The portableelectronic device of claim 12, wherein the first pixel, the secondpixel, the third pixel, and the fourth pixel share a floating diffusionnode in the semiconductor substrate.
 15. An image sensor comprising: afirst pixel and a second pixel, the first pixel including, a firstphotoelectric conversion element in a semiconductor substrate, and thesecond pixel including, a second photoelectric conversion element in thesemiconductor substrate, at least a portion of the first photoelectricconversion element covering at least a portion of the secondphotoelectric conversion element in a vertical direction, the portion ofthe second photoelectric conversion element being less than the entiresecond photoelectric conversion element and the portion of the firstphotoelectric conversion element being less than the entire firstphotoelectric conversion element.
 16. The image sensor of claim 15,further comprising: a third pixel including a third photoelectricconversion element in the semiconductor substrate, at least a portion ofthe third photoelectric conversion element covering the portion of thefirst photoelectric conversion element and the portion of the secondphotoelectric conversion element.
 17. The image sensor of claim 16,wherein the first photoelectric conversion element, the secondphotoelectric conversion element and the third photoelectric conversionelement are at different depths in the semiconductor substrate.
 18. Theimage sensor of claim 15, wherein the first pixel and the second pixelare in a same row.
 19. The image sensor of claim 15, wherein thesemiconductor substrate is doped with one of a first impurity and asecond impurity, and the first pixel and the second pixel are doped withanother of the first impurity and the second impurity.